ECC Memory & DDR5 Channel Diagnostics
Isolating transient correctable memory errors from persistent channel degradation across multi-socket NUMA topologies.
Operational Context:
When memory error rates exceed baseline thresholds, structured isolation identifies whether the issue stems from socket seating, DIMM trace degradation, or thermal micro-swings.
Investigation Sequence:
- Review BMC System Event Logs (SEL) for specific socket and channel DIMM slot designations.
- Check memory temperature telemetry to ensure DIMMs operate within safe thermal thresholds.
- Execute a cold boot memory retraining sequence to re-calibrate signal timing across DDR5 channels.

